(1) Field of the Invention
The present invention relates to a logic circuit and, more particularly, to a logic circuit to which a digital value of multi-level logic data is inputted and from which a digital value of two-valued logic data is outputted.
(2) Description of the Prior Art
Only the input part is often made to have a multi-level logic input configuration and this is done for enabling to input data of as many different states as possible within the limited number of chip pins of an LSI (Large-scale integrated circuit). For example, where there are provided two input pins for receiving the input signals of three levels including an intermediate level (M) in addition to a low level (L) and a high level (H), it is possible to have them deal with nine different combinations of inputs (3.times.3=9), which combinations are larger than twice as compared to those in an ordinary two-level (or two-valued) input configuration (2.times.2=4).
Conventionally, as shown in FIG. 1A, the inputs V.sub.I and each of the threshold values V.sub.1, V.sub.2 are compared by a comparator 1 and a comparator 2 which have different threshold values with each other and the results are outputted to output terminals V.sub.01 and V.sub.02 as two-valued logic data. FIG. 1B is a truth table for such inputs and outputs.
As such comparators 1 and 2, there have often been used a pair of differential amplifiers or a pair of inverters having different threshold values with each other. In such arrangement, in order to be able to achieve three different level inputs, that is, to have the input connected to ground (L), allowed to be in an open state (M), and connected to a power source (H), a bias voltage corresponding to the potential of intermediate level (M) is applied by resistors R.sub.1 and R.sub.2.
Generally, in the case of the comparator using a differential amplifier, it is necessary that the constant current be always supplied to the comparators and this results in such disadvantages that power is always consumed accordingly and also that such circuitry as a load circuit becomes complex in order to secure an appropriate dynamic range in the outputs.
In the case of the inverters having different threshold values, power is not consumed in the CMOS inverters when the input level applied thereto is "L" or "H". However, there is a defect that, when the input level applied thereto is at the intermediate level (M), an N-channel transistor and a P-channel transistor constituting the inverter are caused to be turned on at the same time thereby allowing a large current to flow therein as the so-called "through current".